1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, a method of relieving the same, and a method of testing the same, in particular, an LSI equipped with a plurality of memory circuits and a built-in replacement analysis circuit which generates memory relief information, a method of relieving the same, and a method of testing the same, which are used for LSIs equipped with a plurality of SRAMs or the like.
2. Description of the Related Art
Recently, to deal with increase in defect rate of LSIs caused by miniaturization in the manufacturing process of LSIs, there is a tendency of equipping even memory circuits of relatively small capacity with a redundancy (R/D) mechanism. If R/D rate of the memory increases, additional circuits are provided, such as a fuse circuit, which stores relief information in a fuse, a comparison circuit, a BIRA (built-in replacement and analyzing) circuit which generates memory relief information, etc.
In prior art, an LSI equipped with a plurality of SRAMs has a structure in which one comparison circuit, one BIRA circuit, and one fuse circuit are provided for each SRAM, to simultaneously perform test and replacement analysis for the SRAMs for the purpose of efficiently performing test. However, this increases the size of additional circuits. Therefore, there is the problem that the number of the additional circuits also increases as the number of memory circuits mounted on one LSI chip increases.
Jpn. Pat. Appln. KOKAI Pub. No. 2003-319298 discloses a technique of performing redundant analysis for a plurality of memory circuits one by one (serially), which share a BIST (built-in test) circuit and a BIRA circuit. Further, although Jpn. Pat. Appln. KOKAI Pub. No. 2003-151293 discloses a technique of replacing the same line in the DRAM, the technique cannot be used for dealing with a plurality of memories.